max planck institut
informatik
mpii logo Minerva of the Max Planck Society
 

Ziyad Hanna (Intel), Logic Verification Challenges at System Level Design at Intel

Moore's Law continues to drive an exponential increase in the number of transistors that can be integrated onto a single microprocessor or system chip. Computer architects and system designers continue to look for ways to take advantage of this to produce ever more complex microprocessors. However, it has become evident that logic correctness is one of the main challenges, perhaps even the most important challenge, that computer engineers usually face during the design and validation of such systems.

In this talk, we will highlight the main changes in the Microprocessor and system level design and validation, and present thoughts and research directions to cope with them, including raining the abstraction level of modeling to higher level, exploring new prevention and detection technologies, and raising the level of reasoning technologies above Boolean to include higher logic theories. Moore's Law continues to drive an exponential increase in the number of transistors that can be integrated onto a single microprocessor or system chip. Computer architects and system designers continue to look for ways to take advantage of this to produce ever more complex microprocessors. However, it has become evident that logic correctness is one of the main challenges, perhaps even the most important challenge, that computer engineers usually face during the design and validation of such systems.

In this talk, we will highlight the main changes in the Microprocessor and system level design and validation, and present thoughts and research directions to cope with them, including raining the abstraction level of modeling to higher level, exploring new prevention and detection technologies, and raising the level of reasoning technologies above Boolean to include higher logic theories.