@inproceedings{StShPa_10CORALS,
TITLE = {Cache Oblivious Parallelograms in Iterative Stencil Computations},
AUTHOR = {Strzodka, Robert and Shaheen, Mohammed and Pajak, Dawid and Seidel, Hans-Peter},
LANGUAGE = {eng},
ISBN = {978-1-4503-0018-6},
DOI = {10.1145/1810085.1810096},
PUBLISHER = {ACM},
YEAR = {2010},
DATE = {2010},
ABSTRACT = {We present a new cache oblivious scheme for iterative stencil computations that <br>performs beyond system bandwidth limitations as though gigabytes of data could <br>reside in an enormous on-chip cache. We compare execution times for 2D and 3D <br>spatial domains with up to 128 million double precision elements for constant <br>and variable stencils against hand-optimized naive code and the automatic <br>polyhedral parallelizer and locality optimizer PluTo and demonstrate the clear <br>superiority of our results. The performance benefits stem from a tiling <br>structure that caters for data locality, parallelism and vectorization <br>simultaneously. Rather than tiling the iteration space from inside, we take an <br>exterior approach with a predefined hierarchy, simple regular parallelogram <br>tiles and a locality preserving parallelization. These advantages come at the <br>cost of an irregular work-load distribution but a tightly integrated <br>load-balancer ensures a high utilization of all resources.},
BOOKTITLE = {ICS '10: Proceedings of the 24th ACM International Conference on Supercomputing},
PAGES = {49--59},
ADDRESS = {Tsukuba, Ibaraki, Japan},
}